(1) Field of the Invention
The invention relates to Flash memory cell devices, and more particularly, to a parasitic surface transfer transistor (PASTT) Flash memory cell for bi-level and multi-level NAND Flash memory structures and a method of manufacture thereof.
(2) Description of the Prior Art
As the blooming market of multi-media expands, high-density Flash memories are being applied to mass storage applications such as handy terminals, solid state cameras, and PC cards. Flash memories have many advantages, such as, fast access time, low power dissipation, and robustness. However, in order to gain greater market access, several requirements must be satisfied. First, the bit cost must be made lower. Bit cost is estimated at about $1.00 per megabyte by the 2000. Second, Flash memories must have high reliability. The target reliability, which is related to program/erase endurance and data retention, is a ten-year data retention time after one million program/erase cycles. Finally, high speed programmability, on the order of one microsecond per byte, and single 2.5 to 3.3 Volt power supply operation are emerging requirements.
Referring now to FIG. 1, a prior art EEPROM structure is illustrated. This Flash memory structure is a NAND configuration. A NAND configured EEPROM allows the individual cell size to be reduced without scaling the design or layout rules. The number of bit line contacts is reduced by connecting each Flash cell in series. In addition, such a prior art NAND-structure EEPROM would use a bi-polarity, Fowler-Nordheim tunneling program/erase method to achieve high reliability and high-speed programming.
In the example NAND structure, four Flash memory cells 46, 50, 54, and 58 are connected in series between the bit line 10 selection transistor, SLG1 42, and the source 14 selection transistor, SLG2 62. In the case of a bi-level memory system, the state of each cell in the array is either xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d. To determine the particular state of an individual cell, the cell must be selected and tested. In the example case, the contents of the Flash cell 50 are read. To read the cell 50, the gate of the bit line selection transistor, SLG1 42, is biased to 5V and turned ON. The source selection transistor, SLG2 62, is likewise turned ON. The non-selected word lines, WORDLINE1 22, WORDLINE3 30, and WORDLINE4 34 are all biased to 5V and, therefore, turned ON. WORDLINE2 26 is then biased to a reading voltage, which is a voltage between the xe2x80x9c1xe2x80x9d state threshold voltage (Vth) and the xe2x80x9c0xe2x80x9d state threshold voltage. For example, if the xe2x80x9c0xe2x80x9d state (erased) threshold voltage of the Flash cell is xe2x88x921 Volt and the xe2x80x9c1xe2x80x9d state (programmed) threshold voltage of the Flash cell is 2 Volts, then the reading voltage may be 0.5 Volts. If WORDLINE2 26 is biased to 0.5 Volts, then cell 50 will only conduct if it is in the xe2x80x9c0xe2x80x9d state. The cell 50 will not conduct if it is in the xe2x80x9c1xe2x80x9d state. Current flow-or voltage discharge on the BITLINE-1 10 node can detect the state of the cell 50 based on this setup.
Referring now to FIG. 2, a graphical representation of the bi-level performance of the prior art NAND Flash structure is shown. The Vth distribution of the bi-level programming scheme is illustrated. The xe2x80x9c0xe2x80x9d level state is defined as the erased state of a cell in which the Vth level is controlled only by the inherent properties of the cell transistor without any floating gate charge storage. In this example, the Flash cells in the memory device exhibit a distribution 70 of xe2x80x9c0xe2x80x9d level voltage thresholds of between about xe2x88x920.5 Volts and xe2x88x923 Volts.
The xe2x80x9c1xe2x80x9d level state is defined as the programmed state for a cell in which the Vth value is modified by the presence of negative charge on the floating gate. In this example, the Flash cells in the memory device exhibit a distribution 74 of xe2x80x9c1xe2x80x9d level voltage thresholds of between about 0.5 Volts and 3.5 Volts covering a range R21. As described above, during a reading operation, the unselected cells in the bit-line series of the cell being read must be turn ON. The unselected cells must be driven with a gate voltage 78 that is greater than-the highest xe2x80x9c1xe2x80x9d level voltage threshold so that all the unselected cells are guaranteed to be in the ON state during a read. Note that a wide xe2x80x9c1xe2x80x9d level range R21 is desirable for insuring easy and fast programming of the cell. However, a wide range makes it difficult to insure that all unselected cells will be ON during reads to the selected cell. It is desirable to maintain a wide R21 value while providing a maximum separation of the xe2x80x9c1xe2x80x9d level distribution 74 and the unselected gate voltage distribution 78.
It has been found that the cost per bit of Flash memory devices can be significantly reduced through the use of multi-level schemes in which more than two levels are encoded onto the threshold voltages of the cells. For example, a four-level scheme, wherein xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d, xe2x80x9c2xe2x80x9d, and xe2x80x9c3xe2x80x9d are encoded into a sequence of escalating threshold voltage values, has been shown to reduce the required area for a fixed memory size by about 60%. In such a system, the programming technique allows the amount of floating gate charging to be controlled such that discrete Vth values are attained for each level state. The xe2x80x9c0xe2x80x9d state remains the erased or inherent Vth state.
Referring now to FIG. 3, the Vth distribution for a four-level NAND EEPROM scheme is illustrated. Again, the xe2x80x9c0xe2x80x9d level reflects the non-charged state of a cell and exhibits a fairly wide distribution 82 below 0 Volts. However, the xe2x80x9c1xe2x80x9d level distribution 86 must be much narrower than in the bi-level system so that the additional xe2x80x9c2xe2x80x9d and xe2x80x9c3xe2x80x9d levels can be included.
Note that the xe2x80x9c1xe2x80x9d, xe2x80x9c2xe2x80x9d, and xe2x80x9c3xe2x80x9d levels are narrowly distributed 86, 90, and 94 and have tight ranges of R1, R2, and R3, respectively. For example, each range R1, R2, and R3 is about 0.6 Volts. Further, the levels are closely spaced with spacings S1 and S2 of about 0.8 Volts. Finally, the xe2x80x9c3xe2x80x9d level 94 must be spaced S3 from the unselected gate voltage distribution 100 by about 0.6 Volts to insure correct operation. It is essential that the entire range of levels xe2x80x9c1xe2x80x9d, xe2x80x9c2xe2x80x9d, and xe2x80x9c3xe2x80x9d be encoded in less than about 4 Volts to insure proper operation during cell reads and, particularly, to insure that the unselected cell voltage of about 5 Volts will turn ON the highest xe2x80x9c3xe2x80x9d level cells. This very tight spacing and distribution scheme causes cell programming to be very slow. This is because the programmed cells must be verified within these tight level windows. In addition, data retention failures are greater because of these narrow level ranges.
To avoid the problems caused by the four-level scheme while achieving the advantage of smaller area, a side-wall transfer-transistor cell (SWATT) multi-level NAND Flash EEPROM has been developed. This technique provides low Vth transistors in parallel with each Flash cell. These low Vth transistors are guaranteed to turn ON at the unselected gate voltage regardless of the programmed state of their cell. This means that a wider voltage distribution can be designed for the xe2x80x9c1xe2x80x9d, xe2x80x9c2xe2x80x9d, and xe2x80x9c3xe2x80x9d levels. Programming speed and data retention are improved while achieving a small cell size of about 0.67 microns2 for a 0.35 micron design rule. However, as will be seen in the following analyze, the SWATT Flash cell scheme has several disadvantages.
Referring now to FIG. 4, a cross-section of a partially completed SWATT Flash memory device is shown. At this stage of the processing sequence, a stack comprising a tunneling oxide layer 124, a polysilicon layer 128, and a cap oxide layer 132 has seen deposited overlying the semiconductor substrate 120. The stack 124, 128, and 132 has been patterned to define the floating gates for the Flash cells. Trenches 140 for shallow trench isolations (STI) have been etched into the semiconductor substrate 120. Finally, a trench oxide filling layer 136 has been deposited.
Referring now to FIG. 5, the trench oxide filling layer 136 is etched back to complete the STI 136. The cap oxide layer 132 is removed during the etch back process. The trench oxide filling layer 136 is etched back to reveal a portion of the trench side-walls 144 where the transfer-transistors will be formed. A boron ion implantation 146 is then performed to adjust the Vth of the planned side-wall transfer-transistors. Note that the boron ion implantation 146 must be performed using an angled implantation to effectively implant the semiconductor substrate 120 in the region where the side-wall transfer-transistors are planned 144.
Referring now to FIG. 6, an ONO layer 148 and a second polysilicon layer 152 are deposited. The control gate over the floating gate of each cell is thus created. In addition, the transfer-transistor gates 164 are formed comprising the second polysilicon layer 152 overlying the exposed semiconductor substrate 120 on the side-walls of the trenches 164 with the ONO layer 148 therebetween.
As discussed above, the presence of the side-wall transfer-transistors provides a significant advantage for the Flash cells so constructed. However, there are several significant disadvantages to the SWATT device and process method used to fabricate it. It is important that the threshold voltage (Vth) of the side-wall transfer-transistor be carefully controlled. The dominant parameters determining the Vth of the SWATT devices are the boron concentration in the trench side-wall area, the thickness of the ONO layer 148 in the SWATT area, and the channel width of the SWATT cell.
While the boron concentration can be carefully controlled, the ONO thickness and channel width cannot be so carefully controlled. For example, the ONO thickness will be affected by the first oxide layer thickness in the ONO stack 148. This first oxide layer thickness depends upon the crystal orientation of the top corner of the STI trench and is strongly dependent upon the slope of the trench. This means that the Vth of the SWATT cell will be controlled by the STI module process, including the trench etching, trench oxide etch back, and liner oxidation processes. The STI module processes are not designed to achieve such precise control. Further, the Vth will be determined by the channel width of the SWATT cell. The dominant factor in this parameter is the trench oxide filling layer 136 etch back process. It is difficult to control the etch back process and, therefore, the channel width of the SWATT cell will vary significantly.
Several prior art inventions describe NAND-type Flash EEPROM memories, devices, and process methods. U.S. Pat. No. 6,023,085 to Fang discloses a method of forming a NAND-type Flash memory device. The core region of the integrated circuit contains memory cells and selection transistors. The periphery region contains low and high voltage transistors. The method teaches a technique to form select transistors having thicker gate oxide than the tunneling oxide used in the memory cells. The selection transistors may or may not comprise the stacked gate used in the memory cells. U.S. Pat. No. 6,064,611 to Tanaka et al teaches a NAND-type Flash memory device. The read circuit includes a means of pre-charging the bit-line through a transistor. During read sensing, this transistor is turned OFF. A multi-level NAND memory-block is illustrated. U.S. Pat. No. 6,122,193 to Shibata et al discloses a data latch circuit that facilitates encoding data from binary to four-level for storage in a four-level memory.
A principal object of the present invention is to provide an effective and very manufacturable Flash EEPROM memory device.
A further object of the present invention is to spread the NAND Flash multi-level voltage thresholds across a wider voltage range to thereby improve programming speed and data retention.
Another yet further object of the present invention is to allow faster programming by reducing the number of program/verify cycles.
Another yet further object of the present invention is to achieve a small layout area and a low per bit cost.
Another yet further object of the present invention is to integrate the parasitic surface transfer-transistors into the manufacturing process such that good control of the transfer-transistor voltage threshold is achieved.
In accordance with the objects of this invention, a new Flash memory cell device with a parasitic surface transfer transistor (PASTT) is achieved. The device comprises, first, a semiconductor substrate. The semiconductor substrate further comprises an active area and an isolation barrier region. A source junction is in the active area. A drain junction is in the active area. A cell channel is in the active area extending from the drain junction to the source junction. A parasitic channel is in the active area on the top surface of the semiconductor substrate extending from the drain junction to the source junction. The parasitic channel is bounded on one side by the isolation barrier region and on another side by the cell channel. A floating gate comprises a first conductive layer overlying the cell channel with a tunneling oxide layer therebetween. The floating gate does not overlie the parasitic channel. A control gate comprises a second conductive layer overlying the floating gate with an interlevel dielectric layer therebetween. A parasitic surface transfer-transistor (PASTT) gate comprises the second conductive layer overlying the parasitic channel with the interlevel dielectric layer therebetween. The PASTT gate inverts the parasitic channel to turn ON the PASTT device at a parasitic threshold voltage.
Also in accordance with the objects of this invention, a new method to form a Flash memory device with Flash memory cells and parasitic surface transfer transistors (PASTT) in the manufacture of an integrated circuit device is achieved. A tunneling oxide layer is deposited overlying a semiconductor substrate. A first conductive layer is deposited overlying the tunneling oxide layer. The first conductive layer and the tunneling oxide layer are patterned to define the cell width edges of floating gates for planned Flash memory cells and to expose the semiconductor substrate where shallow trench isolations are planned. Temporary sidewall spacers are formed on the cell width edges of the first conductive layer. The exposed semiconductor substrate is etched to form trenches for the planned shallow trench-isolations. A trench filling oxide layer is deposited overlying the first conductive layer and the temporary sidewall spacers and filling the trenches. The trench filling oxide layer is polished down to complete the shallow trench isolations and to thereby define active areas in the semiconductor substrate. The temporary sidewall spacers are removed to thereby expose the active areas between the shallow trench isolations and the cell width edges of the first conductive layer. The exposed active areas form parasitic channels and the unexposed active areas form cell channels. The semiconductor substrate is ion implanted to thereby adjust the threshold voltages of the Flash memory cells and the PASTT devices. An interlevel dielectric layer is deposited overlying the first conductive layer and the parasitic channels. A second conductive layer is deposited overlying the interlevel dielectric layer. Parasitic transistor gates are formed where the second conductive layer overlies the parasitic channels with the interlevel dielectric layer therebetween. The second conductive layer, the interlevel dielectric layer, the first conductive layer, and the tunneling oxide are patterned to thereby form control gates and to define the cell length edges of the floating gates for the Flash memory cells. Floating gates are formed where the first conductive layer overlies the cell channels with the tunneling oxide layer therebetween. Control gates are formed where the second conductive layer overlies the floating gates with the interlevel dielectric layer therebetween. Ions are implanted into the semiconductor substrate to form source and drain junctions to complete the Flash memory cells and the PASTT devices said in the manufacture of the Flash memory device.